Synchronous commutation DC-DC converter

ABSTRACT

A synchronous commutation DC-DC converter comprises a current detection transformer ( 51 ) for detecting currents (I Q1 , I Q2 ) flowing through the primary circuit, first and second DC bias power sources ( 53, 54 ) generating bias voltages (V BS1 , V BS2 ) larger than the voltage corresponding to the exciting current of a transformer ( 4 ), and first and second comparators ( 55, 57 ) for driving first and second commutation MOS-FETs ( 7, 8 ) when the detection voltage (V DT ) of a current detection resistor ( 52 ) exceeds the bias voltages (V BS1 , V BS2 ) of the first and second DC bias power sources ( 53, 54 ). Since each commutation MOS-FET ( 7, 8 ) in the secondary circuit is driven in synchronism with the currents (I Q1 , I Q2 ) of the primary circuit from which the exciting current component of the transformer ( 4 ) is removed, it is possible to minimize switching loss of each commutation MOS-FET ( 7, 8 ) in the secondary circuit and enhance conversion efficiency of the synchronous commutation DC-DC converter.

TECHNICAL FIELD

This invention relates to a DC-DC converter of synchronous rectificationtype which can improve the conversion efficiency by reduction inswitching loss in a secondary side circuit of the converter.

BACKGROUND OF THE INVENTION

A DC-DC converter of synchronous rectification type is known as aswitching power source device of high conversion efficiency whichcomprises a transformer, primary and secondary side circuits of thetransformer. The primary side circuit comprises at least one mainswitching element and a primary winding of the transformer connected inseries with a DC power source. The secondary side circuit comprises asecondary winding of the transformer electromagnetically coupled to theprimary winding, and at least one rectifying switching element connectedbetween the secondary winding and a load. The main switching element isturned on and off during the switching operation, and the rectifyingswitching element is driven synchronously with operation of the mainswitching element to supply a DC output to the load through thesecondary side circuit. A prior art DC-DC converter of synchronousrectification type shown in FIG. 14, comprises first and second mainMOS-FETs 2 and 3 as first and second main switching elements connectedin series to a DC power source 1; a primary winding 4 a of a transformer4 connected between a junction of first and second main MOS-FETs 2 and 3and a negative terminal of DC power source 1 through a current resonancecapacitor 5 connected in series to primary winding 4 a of transformer 4;a voltage pseudo resonance capacitor 6 connected between drain andsource terminals of first main MOS-FET 2; first and second rectifyingMOS-FETs 7 and 8 as first and second rectifying switching elementsconnected to secondary windings 4 b and 4 c of transformer 4; first andsecond output rectifying diodes 9 and 10 connected to source and drainterminals of respectively first and second rectifying MOS-FETs 7 and 8;and an output smoothing capacitor 11 connected between a center tap ofsecondary windings 4 b and 4 c and each source terminal of first andsecond rectifying MOS-FETs 7 and 8. Accordingly, a primary circuit iscomposed of first and second main MOS-FETs 2 and 3, primary winding 4 aof transformer 4, current resonance capacitor 5 and voltage pseudoresonance capacitor 6, and a secondary circuit is composed of secondarywindings 4 b and 4 c of transformer 4, first and second rectifyingMOS-FETs 7 and 8, first and second output rectifying diodes 9 and 10 andoutput smoothing capacitor 11.

Transformer 4 comprises a drive winding 4 d electromagnetically coupledwith primary winding 4 a, and a leakage inductance 4 e as a currentresonance reactor or coil connected in series to primary winding 4 a.Drive winding 4 d supplies active DC power to a drive power source portV_(CC) of control circuit 21 through a rectifying diode 12 and asmoothing capacitor 13. Connected between a positive terminal of DCpower source 1 and smoothing capacitor 13 is a trigger resistor 14 forintroducing electric current from DC power source 1 to smoothingcapacitor 13 at the time of start-up of the converter to electricallycharge smoothing capacitor 13 so that control circuit 21 startsoperation when smoothing capacitor 13 is charged to a certain voltagelevel. A charge pump circuit is made up of a rectifying diode 15 and asmoothing capacitor 16 connected in series between trigger resistor 14and a junction of first and second main MOS-FETs 2 and 3 to provide DCpower between power source terminals V_(B) and V_(S) on the high voltageside of control circuit 21. An output voltage detector 17 is connectedto both ends of an output smoothing capacitor 11 to detect DC outputvoltage V_(O), and a photo-diode 19 of a photo-coupler 18 is connectedbetween center tap of secondary windings 4 b and 4 c and output voltagedetector 17. A detection output signal of photo-diode 19 is given to aphoto-transistor 20 of photo-coupler 18 connected to a feedback signalinput terminal V_(FB) of control circuit 21.

Control circuit 21 comprises an oscillator 22; a D-flip flop (DFF) 23for receiving outputs from oscillator 22; a first time-adding circuit 24connected to one output terminal of DFF 23; a first buffer amplifier 25for receiving outputs from first time-adding circuit 24; a secondtime-adding circuit 26 connected to the other output terminal of DFF 23;a level shifter 27 for receiving outputs from second time-adding circuit26; and a second buffer amplifier 28 for receiving outputs from levelshifter 27. Oscillator 22 generates pulse signals of the frequency whichcan vary in response to the level of output voltage V_(O), namely outputsignal from output voltage detector 17 given to feedback input terminalV_(FB) of control circuit 21 through photo-coupler 18. DFF 23 receivespulse signals from oscillator 22 to produce first and second drive pulsesignals V_(G1) and V_(G2) inverted from V_(G1) at one and the otheroutput terminals. First and second time-adding circuits 24 and 26 add adead time of a constant span to respectively first and second drivepulse signals V_(G1) and V_(G2) from DFF 23. First buffer amplifier 25receives dead time-added first drive pulse signals V_(G1) from firsttime-adding circuit 24 and applies them to gate terminal of first mainMOS-FET 2. Dead time-added second drive pulse signals V_(G2) isforwarded from second time-adding circuit 26 to level shifter 27 whichelevates reference voltage level of dead time-added second drive pulsesignals V_(G2) from ground level to voltage level at a junction betweena source terminal of first main MOS-FET 2 and a drain terminal of secondmain MOS-FET 3. Second buffer amplifier 28 amplifies second drive pulsesignals V_(G2) from level shifter 27 and forwards them to gate terminalof second main MOS-FET 3. This causes control circuit 21 to modulatefrequency of first and second drive pulse signals V_(G1) and V_(G2) (PFMor Pulse Frequency Modulation) in response to voltage level of outputsignals detected by output voltage detector 17, and forwards them toeach gate terminal of first and second main MOS-FETs 2 and 3 whichtherefore can alternately be turned on and off with the frequencycorresponding to voltage level of output signals detected by outputvoltage detector 17.

Gate terminal of first main MOS-FET 2 is connected through a firstcapacitor 29 and a first pulse transformer 31 to a gate terminal of afirst rectifying MOS-FET 7 so that first drive pulse signals V_(G1) fromcontrol circuit 21 is supplied through first capacitor 29 to a primarywinding 32 of first pulse transformer 31 whose secondary winding 33produces to gate terminal of first rectifying MOS-FET 7 firstsynchronous drive pulse signals V_(SC1) of the similar or same waveformto those of first drive pulse signals V_(G1). Also, gate terminal ofsecond main MOS-FET 3 is connected through a second capacitor 30 and asecond pulse transformer 34 to a gate terminal of a second rectifyingMOS-FET 8 so that second drive pulse signals V_(G2) from control circuit21 is supplied through second capacitor 30 to a primary winding 35 ofsecond pulse transformer 34 whose secondary winding 36 produces to gateterminal of second rectifying MOS-FET 8 second synchronous drive pulsesignals V_(SC2) of the similar or same waveform to those of second drivepulse signals V_(G2). This causes first and second rectifying MOS-FETs 7and 8 on the secondary side to be turned on and off in synchronizationwith the on and off operation of first and second main MOS-FETs 2 and 3on the primary side to generate to a load not shown DC output voltageV_(O) of substantially constant level between output terminals of thesecondary circuit.

In operation of the DC-DC converter of synchronous rectification typeshown in FIG. 14, when a power switch not shown therein is turned on, anelectric current flows from DC power source 1 through trigger resistor14 to smoothing capacitor 13 to electrically charge smoothing capacitor13. When charged voltage in smoothing capacitor 13 comes up to astart-up level for control circuit 21, it starts the operation. At themoment, control circuit 21 produces first and second drive pulse signalsV_(G1) and V_(G2) to each gate terminal of first and second mainMOS-FETs 2 and 3 to start turning them on and off. When second mainMOS-FET 3 is turned on, a winding current I_(Q2) runs from DC powersource 1 through second main MOS-FET 3, leakage inductance 4 e andprimary winding 4 a of transformer 4 and current resonance capacitor 5to DC power source 1 of primary side circuit to electrically chargecurrent resonance capacitor 5. Winding current I_(Q2) is a compositecurrent of excitation current through primary winding 4 a of transformer4 and resonance current of the resonance frequency determined bycapacitance of current resonance capacitor 5 and leakage inductance 4 eof transformer 4. As second rectifying MOS-FET 8 is concurrently turnedon synchronously with turning-on operation of second main MOS-FET 3, anelectric current I_(S2), which has substantially same resonancefrequency as that of resonance current, flows from second secondarywinding 4 c of transformer 4 through a parallel circuit of secondrectifying diode 10 and second rectifying MOS-FET 8 to output smoothingcapacitor 11 and load.

When second main MOS-FET 3 is switched off while winding current I_(Q2)flows through primary side circuit, voltages V_(Q1) between drain andsource terminals of first main MOS-FET 2 and V_(Q2) between drain andsource terminals of second main MOS-FET 3, provide pseudo resonancevoltage of the resonance frequency determined by capacitance of voltagepseudo resonance capacitor 6 and composite inductance of leakageinductance 4 e and excitation inductance not shown of transformer 4. Atthe same time, excitation current, which has passed through primarywinding 4 a of transformer 4 and second main MOS-FET 3, is divertedtoward a pseudo diode not shown but appearing between drain and sourceterminals of first main MOS-FET 2. When first main MOS-FET 2 is turnedon while excitation current is diverted through pseudo diode of firstmain MOS-FET 2, this excitation current naturally decreases, and then,the polarity is inverted to cause electric current I_(Q1) to flow fromcurrent resonance capacitor 5 through primary winding 4 a and leakageinductance 4 e of transformer 4 and first main MOS-FET 2 to dischargecurrent resonance capacitor 5. This electric current I_(Q1) throughfirst main MOS-FET 2 has the adverse polarity to that of winding currentI_(Q2), and provides a composite current of excitation current throughprimary winding 4 a of transformer 4 and resonance current of theresonance frequency determined by capacitance of current resonancecapacitor 5 and leakage inductance 4 e of transformer 4. Also, as firstrectifying MOS-FET 7 is turned on synchronously with the turning-onoperation of first main MOS-FET 2, a rectified output current I_(S1),which has substantially same resonance frequency as that of resonancecurrent, flows from first secondary winding 4 b of transformer 4 througha parallel circuit of first rectifying diode 9 and first rectifyingMOS-FET 7 to output smoothing capacitor 11 and load.

When first main MOS-FET 2 is switched off while electric current I_(Q1)flows through primary side circuit, voltages V_(Q1) between drain andsource terminals of first main MOS-FET 2 and V_(Q2) between drain andsource terminals of second main MOS-FET 3, provide pseudo resonancevoltage of the resonance frequency determined by capacitance of voltagepseudo resonance capacitor 6 and composite inductance of leakageinductance 4 e and excitation inductance not shown of transformer 4. Atthe same time, excitation current, which has passed through primarywinding 4 a of transformer 4 and first main MOS-FET 2, is divertedtoward a pseudo diode not shown but appearing between drain and sourceterminals of second main MOS-FET 3. When second main MOS-FET 3 is turnedon while excitation current is diverted through pseudo diode of secondmain MOS-FET 3, this excitation current naturally decreases, and then,the polarity is inverted to cause electric current I_(Q2) to flowthrough second main MOS-FET 3. FIGS. 15(A), 15(B) and 15(C) indicaterespectively waveforms of voltage V_(Q1) between source and drainterminals of first main MOS-FET 2, electric current I_(Q1) through firstmain MOS-FET 2, and electric current through first secondary winding 4 bof transformer 4.

After that, the above-mentioned synchronous rectifying operation isrepeated to produce DC output voltage V_(O) of substantially constantlevel from secondary side circuit to load. As switching frequency offirst and second main MOF-FETs 2 and 3 is higher than resonancefrequency determined by capacitance of current resonance capacitor 5 andleakage inductance 4 e of transformer 4, DC output to load can becontrolled by increasing switching frequency of first and second mainMOS-FETs 2 and 3. A DC-DC converter of synchronous rectification typesimilar to the foregoing is shown by for example Japanese PatentDisclosure No. 2000-23455 (Page 5, FIG. 3).

Now, rectified output currents I_(S1) and I_(S2) flowing throughsecondary side circuit of transformer 4 do not exactly synchronize withthe on-period of first and second main MOS-FETs 2 and 3 of primary sidecircuit as shown in FIGS. 15(C) and 15(A), since first and secondrectifying MOS-FETs 7 and 8 of secondary side circuit are turned onsynchronously with the turning-on of first and second main MOS-FETs 2and 3 in DC-DC converter shown in FIG. 14. Accordingly, adverse currentoccurs which flows from output smoothing capacitor 11 toward first andsecond secondary windings 4 b and 4 c of transformer 4 because first andsecond rectifying MOS-FETs 7 and 8 are turned on during the period of noelectric current through first and second output rectifying diodes 9 and10 of secondary side circuit. This adverse current provides acirculating current which reciprocates between primary and secondaryside circuits, and further disadvantageously incurs unnecessaryswitching loss through first and second main MOS-FETs 2 and 3 on primaryside and first and second rectifying MOS-FETs 7 and 8, therebydetrimentally reducing the conversion efficiency in DC-DC converter.

Accordingly, an object of the present invention is to provide a DC-DCconverter of synchronous rectification type capable of improving theconversion efficiency by reducing switching loss in secondary sidecircuit.

SUMMARY OF THE INVENTION

The DC-DC converter of synchronous rectification type according to thepresent invention comprises: at least one main switching element (2, 3)and a primary winding (4 a) of a transformer (4) as a primary sidecircuit connected to a DC power source (1); at least one rectifyingswitching element (7, 8) as a secondary side circuit connected between asecondary winding (4 b, 4 c) of transformer (4) electromagneticallycoupled to primary winding (4 a) and an electric load; a currentdetector (51) for discerning electric current (I_(Q1), I_(Q2)) flowingthrough the primary side circuit to produce a detection voltage (V_(DT))corresponding to the discerned current (I_(Q1), I_(Q2)); biasing means(53, 54) for producing a bias voltage (V_(BS1), V_(BS2)) higher thanvoltage corresponding to excitation current through transformer (4); anda comparator (55, 57) for activating rectifying switching element (7, 8)when current detector (51) produces the detection voltage over biasvoltage (V_(BS1), V_(BS2)) to turn rectifying switching element (7, 8)on in synchronization with switching operation of main switching element(2, 3) in order to supply DC output (V_(O)) from the secondary sidecircuit to the electric load.

When detected voltage (V_(DT)) from current detector (51) exceeds biasvoltage (V_(BS1), V_(BS2)) from biasing means (53, 54) higher thanvoltage corresponding to excitation current through transformer (4),rectifying switching element (7, 8) is turned on synchronously withelectric current (I_(Q1), I_(Q2)) flowing through the primary sidecircuit except excitation current component through transformer (4)deducted by comparator (55, 57). This causes comparator (55, 57) todrive rectifying switching element (7, 8) in proportion to rectifiedoutput current (I_(S1), I_(S2)) flowing through the secondary sidecircuit to prevent power loss resulted from unnecessary circulatingcurrent. Accordingly, the secondary side circuit can control power losscaused by rectifying switching element (7, 8) to a minimal level toimprove conversion efficiency for the DC-DC converter.

The DC-DC converter of synchronous rectification type according toanother embodiment of the invention, comprises a current detector (51)for discerning an electric current (I_(Q1), I_(Q2)) flowing throughprimary side circuit; biasing means (53, 54) for producing a biasvoltage (V_(BS1), V_(BS2)); a ramp signal generator for issuing a rampsignal (V_(RP)) proportional to voltage relative to excitation currentthrough transformer (4); and a comparator (55, 57) for drivingrectifying switching elements (7, 8) when detected voltage (V_(DT)) fromcurrent detector (51) exceeds the superimposed voltage of biased voltage(V_(BS1), V_(BS2)) of biasing means (53, 54) and ramp signal (V_(RP))from ramp signal generator. The DC-DC converter of synchronousrectification type according to still another embodiment of theinvention, comprises a current detector (51) for detecting electriccurrent (I_(Q1), I_(Q2)) flowing through primary side circuit; biasingmeans (53, 54) for producing a bias voltage (V_(BS1), V_(BS2)); a rampsignal generator for issuing a ramp signal (V_(RP)) proportional tovoltage relative to excitation current through transformer (4); and acomparator (55, 57) for driving rectifying switching elements (7, 8)when detected voltage (V_(DT)) from current detector (51) exceeds thesuperimposed voltage of biased voltage (V_(BS1), V_(BS2)) of biasingmeans (53, 54) and ramp signal (V_(RP)) from ramp signal generator.Since ramp signals (V_(RP)) from ramp signal generator have thesubstantially similar voltage waveform to that of excitation currentflowing through primary winding (4 a) of transformer (4), ramp signals(V_(RP)) can be used to cancel or offset excitation current componentcontained in electric current (I_(Q1), I_(Q2)) in primary side circuitdetected by current detector (51). Accordingly, the converter canefficiently drive rectifying switching elements (7, 8) accurately inproportion to rectified output currents (I_(S1), I_(S2)) throughsecondary side circuit.

In the present invention, rectifying switching elements in secondaryside circuit are driven synchronously with electric current in primaryside circuit excluding excitation current through transformer, in otherwords, when detected voltage by current detector exceeds biased voltageby biasing means higher than the voltage corresponding to excitationcurrent through transformer. This causes rectifying switching elementsto operate commensurately to rectified output current flowing throughsecondary side circuit, inhibiting power loss resulted from unnecessarycirculating current to minimize power loss incurred with rectifyingswitching elements in secondary side circuit and improve conversionefficiency in the converter. Providing a ramp signal generator in theconverter for generating ramp signals proportional to voltage relativeto excitation current through transformer, ramp signals from ramp signalgenerator are used to cancel or offset excitation current componentthrough transformer contained in electric current in primary sidecircuit detected by current detector so that rectifying switchingelements can efficiently be driven exactly in proportion to rectifiedoutput current in secondary side circuit. As biasing means may be of anyoptional bias voltage generator capable of producing electric currentlower than excitation current component through transformer, it isadvantageous to adopt biasing means generating the lower biasingvoltage. In particular, if the present invention is applied to a DC-DCconverter of synchronous resonance rectification type, it may utilizerectifying switching elements of lower withstand voltage and lowerimpedance during the on-period to provide an inexpensive DC-DC converterof synchronous rectification type having the extremely high conversionefficiency.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an electric circuit diagram showing a first embodiment of thecurrent-resonant DC-DC converter of synchronous rectification typeaccording to the present invention;

FIG. 2 is a time chart representing the relationships among detectedvoltage on current detection resistor and synchronous drive pulses foreach rectifying MOS-FETs shown in FIG. 1;

FIG. 3 is a time chart of waveforms of a voltage and electric currentsat selected locations;

FIG. 4 is an electric circuit diagram indicating a modified embodimentfrom the DC-DC converter of synchronous rectification type shown in FIG.1;

FIG. 5 is an electric circuit diagram indicating a modified embodimentfrom the DC-DC converter of synchronous rectification type shown in FIG.4;

FIG. 6 is an electric circuit diagram indicating a second embodiment ofthe DC-DC converter of synchronous rectification type according to thepresent invention;

FIG. 7 is a time chart of waveforms of voltages at selected locations inFIG. 6;

FIG. 8 is an electric circuit diagram indicating a third embodiment ofthe DC-DC converter of synchronous rectification type according to thepresent invention;

FIG. 9 is a time chart of waveforms of voltages at selected locations inFIG. 8;

FIG. 10 is an electric circuit diagram indicating a modified embodimentfrom the DC-DC converter of synchronous rectification type shown in FIG.8;

FIG. 11 is an electric circuit diagram indicating a fourth embodiment ofthe DC-DC converter of synchronous rectification type according to thepresent invention;

FIG. 12 is an electric circuit diagram indicating a fifth embodiment ofthe DC-DC converter of synchronous rectification type according to thepresent invention;

FIG. 13 is an electric circuit diagram indicating a modified embodimentof the DC-DC converter of synchronous rectification type according tothe present invention;

FIG. 14 is an electric circuit diagram of an example of prior art DC-DCconverters of synchronous rectification type; and

FIG. 15 is a time chart of waveforms of a voltage and electric currentsat selected locations in FIG. 14.

(1) . . . a DC power source, (2) . . . a first main MOS-FET (a firstmain switching element), (3) . . . a second main MOS-FET (a second mainswitching element), (4) . . . a transformer, (4 a) . . . a primarywinding, (4 b, 4 c) . . . secondary windings, (4 d) . . . a drivewinding, (4 e) . . . a leakage inductance, (5) . . . a current resonancecapacitor, (6) . . . a voltage pseudo resonance capacitor, (7) . . . afirst rectifying MOS-FET (a first rectifying switching element), (8) . .. a second rectifying MOS-FET (a second rectifying switching element),(9) . . . a first output diode, (10) . . . a second output diode, (11) .. . an output smoothing capacitor, (12) . . . a rectifying diode, (13) .. . a smoothing capacitor, (14) . . . a start-up resistor, (15) . . . arectifying diode, (16) . . . a smoothing capacitor, (17) . . . an outputvoltage detector, (18) . . . a photo-coupler, (19) . . . a photo-diode,(20) . . . a photo-transistor, (21) . . . a control circuit, (22) . . .an oscillator, (23) . . . a D-flip flop, (24) . . . a first time-adder,(25) . . . a first buffer amplifier of low voltage side, (26) . . . asecond time-adder, (27) . . . a level shifter, (28) . . . a secondbuffer amplifier of high voltage side, (29) . . . a first capacitor,(30) . . . a second capacitor, (31) . . . a first pulse transformer,(32) . . . a primary winding, (33) . . . a secondary winding, (34) . . .a second pulse transformer, (35) . . . a primary winding, (36) . . . asecondary winding, (37) . . . an additional current resonance capacitor,(38) . . . an additional voltage pseudo resonance capacitor, (39) . . .a current resonance reactor, (51) . . . a current detecting transformer(a current detector), (52) . . . a current detecting resistor, (53) . .. a first DC bias power supply (biasing means), (54) . . . a second DCbias power supply (biasing means), (55) . . . a first comparator (firstcomparing means), (56) . . . a first buffer amplifier, (57) . . . asecond comparator (second comparing means), (58) . . . a second bufferamplifier, (59) . . . a bias power supply, (60) . . . an operationalamplifier (a synchronizing signal generator), (61) . . . a resistor,(62) . . . an integral capacitor, (63) . . . a drive power supply, (64). . . a waveform shaper (waveform shaping means), (65) . . . a shuntcapacitor, (66) . . . a transfer resistor, (67, 68, 70) . . . resistors,(69) . . . a bias power supply.

BEST MODE FOR CARRYING OUT THE INVENTION

Five embodiments of current-resonant DC-DC converter of synchronousrectification type according to the present invention will be describedhereinafter with reference to FIGS. 1 to 12 of the drawings. Samereference symbols are applied to similar portions in FIGS. 1 to 12 tothose shown in FIGS. 14 and 15 omitting explanation therefor.

As shown in FIG. 1, a first embodiment of the DC-DC converter ofsynchronous rectification type according to the present invention,comprises a current detection transformer 51 as current detecting meansfor detecting electric currents I_(Q1), I_(Q2) flowing through primaryside circuit of a transformer 4; a current detecting resistor 52 forconverting electric current detected by detection transformer 51 into acorresponding voltage V_(DT); first and second DC bias power supplies 53and 54 as biasing means for producing bias voltages V_(BS1) and V_(BS2)higher than voltage corresponding to excitation current throughtransformer 4; a first comparator 55 as first comparing means forproducing a first synchronous drive pulse signal V_(SC1) to turn firstrectifying MOS-FET 7 on when detection voltage V_(DT) by currentdetecting resistor 52 to non-inverted input terminal + of firstcomparator 55 exceeds a bias voltage V_(BS1) of first DC bias powersupply 53 applied to inverted input terminal − of first comparator 55; afirst buffer amplifier 56 for directing first synchronous drive pulsesignal V_(SC1) from first comparator 55 to a gate terminal of firstrectifying MOS-FET 7; a second comparator 57 as second comparing meansfor producing a second synchronous drive pulse signal V_(SC2) to turnsecond rectifying MOS-FET 8 on when detection voltage V_(DT) by currentdetecting resistor 52 to an inverted input terminal − of secondcomparator 57 exceeds a bias voltage V_(BS2) of second DC bias powersupply 54 applied to non-inverted input terminal + of second comparator57; and a second buffer amplifier 58 for directing second synchronousdrive pulse signal V_(SC2) from second comparator 57 to a gate terminalof second rectifying MOS-FET 8. Cathode and anode terminals of first DCbias power supply 53 are connected respectively to ground and invertedinput terminal − of first comparator 55. Anode and cathode terminals ofsecond DC bias power supply 54 are connected respectively to ground andnon-inverted input terminal + of second comparator 57. Two black pointsmarked on the right end of current detection transformer 51 denote thata primary winding not shown connected on a line between a junction offirst and second main MOS-FETs 2 and 3 and primary winding 4 a has asame polarity as secondary winding connected between opposite ends ofcurrent detecting resistor 52. Other components than the abovecomponents are substantially similar to those used in DC-DC converter ofsynchronous rectification type shown in FIG. 14 except omission of firstand second capacitors 29 and 30 and first and second pulse transformers31 and 34.

In operation, when second main MOS-FET 3 is turned on, winding currentI_(Q2) flows from DC power source through second main MOS-FET 3, leakageinductance 4 e and primary winding 4 a of transformer 4, currentresonance capacitor 5 to DC power source in primary side circuit.Winding current I_(Q2) is a composite current of excitation currentthrough primary winding 4 a of transformer 4 and resonance current ofresonance frequency determined by capacitance of current resonancecapacitor 5 and leakage inductance 4 e of transformer 4. Winding currentI_(Q2) in primary side circuit is detected by current detectiontransformer 51 to convert detected winding current I_(Q2) into acorresponding detected voltage V_(DT) by current detecting resistor 52.In other words, induced across current detecting resistor 52 is detectedvoltage V_(DT) which fluctuates in proportion to changing level ofcurrent detected by current detection transformer 51 relative to thereference potential of ground zero volt as shown in FIG. 2(A). Detectedvoltage V_(DT) from current detecting resistor 52 is supplied toinverted input terminal − of second comparator 57 which then comparesdetected voltage V_(DT) with bias voltage V_(BS2) of second DC biaspower supply 54 applied to non-inverted input terminal + of secondcomparator 57. When detected voltage V_(DT) on current detectingresistor 52 declines below bias voltage V_(BS2) of second DC bias powersupply 54 as shown in FIG. 2(A), second comparator 57 produces a secondsynchronous drive pulse signal V_(SC2) of high voltage level shown inFIG. 2(B) to gate terminal of second rectifying MOS-FET 8 through secondbuffer amplifier 58 to turn second rectifying MOS-FET 8 on. Accordingly,an electric current I_(S2) substantially similar to the foregoingresonance current flows from second winding 4 c of transformer 4 througha parallel circuit of second output rectifying diode 10 and secondrectifying MOS-FET 8 and output smoothing capacitor 11 to an electricload not shown.

When second main MOS-FET 3 is turned off while electric current I_(Q2)flows, voltages V_(Q1) between drain and source terminals of first mainMOS-FET 2 and V_(Q2) between drain and source terminals of second mainMOS-FET 3 come to pseudo resonance voltage of resonance frequencydetermined by capacitance of voltage pseudo resonance capacitor 6 andcomposite inductance of excitation inductance not shown and leakageinductance 4 e of transformer 4. At the same time, excitation currentflowing through second main MOS-FET 3 and primary winding 4 a oftransformer 4, is diverted toward and through a parasitic diode notshown connected between drain and source terminals of first main MOS-FET2. When first main MOS-FET 2 is turned on while excitation current isdiverted through parasitic diode, excitation current naturallydiminishes, and then, the polarity is inverted so that electric currentI_(Q1) flows through first main MOS-FET 2. In this case, electriccurrent I_(Q1) flowing in primary side circuit has the adverse polarityto electric current I_(Q2) flowing through second main MOS-FET 3, andprovides a composite current of excitation current through primarywinding 4 a of transformer 4 and resonance current of resonancefrequency determined by capacitance of current resonance capacitor 5 andleakage inductance 4 e of transformer 4. Electric current I_(Q1) flowingthrough primary side circuit is detected by current detectingtransformer 51, and then converted into voltage V_(DT) corresponding todetected current amount. In other words, developed across currentdetecting resistor 52 is detected voltage V_(DT) which fluctuates inproportion to changing level of current detected by current detectiontransformer 51 relative to the reference potential of ground zero voltas shown in FIG. 2(A). Detected voltage V_(DT) from current detectingresistor 52 is supplied to non-inverted input terminal + of firstcomparator 55 which then compares detected voltage V_(DT) with biasvoltage V_(BS1) of first DC bias power supply 53 applied to invertedinput terminal − of first comparator 55. When detected voltage V_(DT) oncurrent detecting resistor 52 rises above bias voltage V_(BS1) of firstDC bias power supply 53 as shown in FIG. 2(A), first comparator 55produces a first synchronous drive pulse signal V_(SC1) of high voltagelevel shown in FIG. 2(C) to gate terminal of first rectifying MOS-FET 7through first buffer amplifier 56 to turn first rectifying MOS-FET 7 on.Accordingly, an electric current I_(S1), which has the waveformsubstantially similar to that of the resonance current flows from secondwinding 4 b of transformer 4 through a parallel circuit of first outputrectifying diode 9 and first rectifying MOS-FET 7 and output smoothingcapacitor 10 to load.

When first main MOS-FET 2 is turned off while electric current I_(Q1)flows, voltages V_(Q1) between drain and source terminals of first mainMOS-FET 2 and V_(Q2) between drain and source terminals of second mainMOS-FET 3, come to pseudo resonance voltage of resonance frequencydetermined by capacitance of voltage pseudo resonance capacitor 6 andcomposite inductance of excitation inductance not shown and leakageinductance 4 e of transformer 4. At the same time, excitation currentflowing through first main MOS-FET 2 and primary winding 4 a oftransformer 4, is diverted toward and through a parasitic diode notshown connected between drain and source terminals of second mainMOS-FET 3. When second main MOS-FET 3 is turned on while excitationcurrent is diverted through parasitic diode, excitation currentnaturally diminishes, and then, the polarity is inverted so thatelectric current I_(Q2) flows through second main MOS-FET 3. Hereafter,the above-mentioned synchronous rectification operation is repeated tosupply DC output voltage V_(O) of substantially constant level to loadfrom secondary side circuit. FIGS. 3(A), 3(B) and 3(C) representwaveforms of respectively voltage V_(Q1) between drain and sourceterminals of first main MOS-FET 2, electric current I_(Q1) flowingthrough first main MOS-FET 2 and electric current I_(S1) throughsecondary winding 4 b of transformer 4.

In the first embodiment, current detecting transformer 51 detectselectric currents I_(Q1) and I_(Q2) flowing through primary side circuitof transformer 4, and when detected voltage V_(DT) by current detectingresistor 52 exceeds bias voltage V_(BS1) or V_(BS2) of first or secondDC bias power supply 53 or 54 higher than voltage corresponding toexcitation current through transformer 4, first or second comparator 55or 57 produces first or second synchronous drive pulse signal V_(SC1) orV_(SC2) of high voltage level which turns first or second rectifyingMOS-FET 7 or 8 on. Thus, first and second rectifying MOS-FETs 7 and 8can be turned on or driven synchronously with electric currents I_(Q1)and I_(Q2) flowing in primary side circuit without excitation currentcomponent through transformer 4 and also simultaneously commensuratelywith rectified output currents I_(S1) and I_(S2) flowing in secondaryside circuit to avoid power loss resulted from undesirable circulatingcurrent. This assures that the DC-DC converter of synchronousrectification type can control and minimize power loss caused byoperation of first and second rectifying MOS-FETs 7 and 8 in secondaryside circuit to improve the conversion efficiency. Also, to accomplishcurrent resonance action, the converter can limit voltage borne on firstand second rectifying MOS-FETs 7 and 8 twice or less DC output voltageV_(O) applied on load because DC output voltage V_(O) and superimposedvoltage on secondary winding 4 b or 4 c may simultaneously be applied oneach of first and second rectifying MOS-FETs 7 and 8. Accordingly,adopting MOS-FETs of lower withstand voltage and lower impedance duringthe on-period, the embodiment can provide an inexpensive DC-DC converterof synchronous rectification type having the extremely high conversionefficiency.

The converter shown in FIG. 1 includes first and second comparators 55and 57 for comparing detected voltage V_(DT) on current detectingresistor 52 with bias voltages V_(BS1) and V_(BS2) by first and secondDC biasing power supplies 53 and 54. An alternative of the converter isshown in FIG. 4 wherein first and second DC biasing power supplies 53and 54 are connected in series respectively between current detectingresistor 52 and first comparator 55 and between current detectingresistor 52 and second comparator 57; detected voltage V_(DT) fromcurrent detecting resistor 52 may be shifted to a negative side by biasvoltage V_(BS1) of first DC bias power supply 53 and also to a positiveside by bias voltage V_(BS2) of second DC bias power supply 54 tocompare shifted voltage V_(DT) with ground zero volt in first and secondcomparators 55 and 57. In the DC-DC converter of synchronousrectification type shown in FIGS. 1 and 4, first and second comparators55 and 57 are driven by two power supplies 53 and 54 for respectivelygenerating negative and positive outputs, however, in most practicalcases, they are driven by a power supply for generating a single output.In this view, it would be advisable to connect a further bias powersupply 59 to each reference voltage input terminal of first and secondcomparators 55 and 57 as shown in FIG. 5 to shift reference voltageabove ground zero volt by further bias power supply 59 and up to a levelthat does not exceed any either allowable input voltage limitation offirst and second comparators 55 and 57. Functions and effects performedin either of the embodiments shown in FIGS. 4 and 5 are essentiallysimilar to those effected in the circuit shown in FIG. 1.

The first embodiment may be modified in various ways. For example, in asecond embodiment of the present invention illustrated in FIG. 6, theDC-DC converter of synchronous rectification type comprises, in additionto the converter shown in FIG. 1, an operational amplifier 60 as asynchronizing signal generator for producing pulse signals V_(PL)synchronizing with frequency of voltage generated in secondary winding 4c of transformer 4; and a resistor 61 and an integral capacitor 62incorporated to form an integration circuit together for generating aramp signal V_(RP) whose inclination is inverted every half cycle ofpulse signal V_(PL) from operational amplifier 60 wherein a junction ofresistor 61 and integral capacitor 62 is connected to a junction ofnegative terminal of first DC bias power supply 53 and positive terminalof second DC bias power supply 54. Inverted and non-inverted inputterminals − and + of operational amplifier 60 are connected respectivelyto ground in secondary side circuit and secondary winding 4 c oftransformer 4. In operation, operational amplifier 60 producesrectangular pulse signals V_(PL) of the alternating polarity shown inFIG. 7(B) with frequency of voltage produced on secondary winding 4 c oftransformer 4 so that pulse signals V_(PL) from operational amplifier 60are supplied to integral capacitor 62 through resistor 61 to charge anddischarge integral capacitor 62 with a time constant determined by theproduct of a resistance value of resistor 61 and capacitance of integralcapacitor 62. Accordingly, integral capacitor 62 produces at a junctionof resistor 61 and integral capacitor 62 ramp signals V_(RP) shown inFIG. 7(C) synchronizing with frequency of voltage developed on secondarywinding 4 c of transformer 4. Thus, operational amplifier 60, resistor61 and integral capacitor 62 provide a ramp signal generator forproducing ramp signals V_(RP) proportional to voltage corresponding toexcitation current flowing through primary winding 4 a of transformer 4.Other components in FIG. 6 are substantially similar to those in theconverter shown in FIG. 1.

In the circuit shown in FIG. 6, current detecting transformer 51 detectselectric current I_(Q2) flowing through primary side circuit when secondmain MOS-FET 3 is turned on, and then current detecting resistor 52converts detected electric current I_(Q2) into voltage V_(DT) relativethereto produced across detecting resistor 52 so that detected voltageV_(DT) fluctuates across reference potential of ground zero volt inproportion to electric current detected by current detecting transformer51. Detected voltage V_(DT) is applied to inverted input terminal − ofsecond comparator 57 which compares detected voltage V_(DT) withsuperimposed signal V_(RP)−V_(BS2) because non-inverted input terminal +of second comparator 57 concurrently receives ramp signal V_(RP) shownin FIG. 7(C) from integral capacitor 62 and bias voltage − V_(BS2) fromsecond DC bias power supply 54. In detail, non-inverted input terminal +of second comparator 57 acquires composite voltage V_(RP)−V_(BS2) shownin FIG. 7(D) because ramp signal voltage V_(RP) on integral capacitor 62is shifted to negative side by bias voltage V_(BS2) of second DC biaspower supply 54. When detected voltage V_(DT) on current detectingresistor 52 decreases below composite voltage V_(RP)−V_(BS2) as shown inFIG. 7(D), second comparator 57 produces second synchronous drive pulsesignals V_(SC2) of high voltage level to gate terminal of secondrectifying MOS-FET 8 through second buffer amplifier 58 to turn secondrectifying MOS-FET 8 on.

Meanwhile, current detecting transformer 51 detects electric currentI_(Q1) flowing through primary side circuit when first main MOS-FET 2 isturned on, and current detecting resistor 52 converts the detectedcurrent into commensurate voltage V_(DT). At this moment, developedacross current detecting resistor 52 is voltage V_(DT) shown in FIG.7(A) which moves proportionately to level of current detected by currentdetecting transformer 51 across reference potential of ground zero volt.Voltage V_(DT) on current detecting resistor 52 is applied tonon-inverted input terminal + of first comparator 55 which comparesdetected voltage V_(DT) with superimposed signal V_(RP)+V_(BS1) becauseinverted input terminal − of first comparator 55 concurrently receivesramp signal V_(RP) shown in FIG. 7(C) from integral capacitor 62 andbias voltage V_(BS1) from first DC bias power supply 53. In detail,inverted input terminal − of first comparator 55 acquires compositevoltage V_(RP)+V_(BS1) shown in FIG. 7(D) because ramp signal voltageV_(RP) on integral capacitor 62 is shifted to positive side by biasvoltage V_(BS1) of first DC bias power supply 53. When detected voltageV_(DT) on current detecting resistor 52 increases above compositevoltage V_(RP)+V_(BS1) as shown in FIG. 7(D), first comparator 55produces first synchronous drive pulse signals V_(SC1) of high voltagelevel to gate terminal of first rectifying MOS-FET 7 through firstbuffer amplifier 56 to turn first rectifying MOS-FET 7 on. Otheroperations of main circuits in the DC-DC converter of synchronousrectification type shown in FIG. 6 than the aforesaid operation issubstantially similar to those in the DC-DC converter shown in FIG. 1,and further detailed description on other operations is omitted.

In the second embodiment, voltage waveform of ramp signal V_(RP)appearing at junction between resistor 61 and integral capacitor 62 isapproximately similar to waveform of excitation current flowing throughprimary winding 4 a of transformer 4. Accordingly, superimposed rampsignal V_(RP), bias voltages V_(BS1) and V_(BS2) cooperate to formbetween V_(RP)−V_(BS2) and V_(RP)+V_(BS1) an insensible area where firstand second comparators 55 and 57 do not respond to detected voltageV_(DT) to cancel or offset excitation current component contained inelectric currents I_(Q1) and I_(Q2) through transformer 4 in primaryside circuit when current detecting transformer 51 detects excitationcurrent component. This enables the converter to turn first and secondrectifying MOS-FETs 7 and 8 on in secondary side circuit synchronouslywith only resonance current component in electric currents I_(Q1) andI_(Q2) flowing through primary side circuit. In other words, first andsecond rectifying MOS-FETs 7 and 8 can efficiently be driven accuratelyin proportion to rectified output current I_(S1) and I_(S2) flowingthrough secondary side circuit. Also, as first and second DC biasingpower supplies 53 and 54 may be of any optional bias voltage generatorscapable of producing bias voltages V_(BS1) and V_(BS2) for covering aelectric current range lower than excitation current component throughtransformer 4, it is advantageous to adopt lower biased voltage thanthat in the first embodiment. Not shown, but the second embodiment maybe modified in substantially similar manners as in the first embodimentsshown in FIGS. 4 and 5.

A third embodiment of the DC-DC converter of synchronous rectificationtype shown in FIG. 8, comprises, in addition to the converter shown inFIG. 4, an operational amplifier 60 as a synchronous signal generatorfor producing pulse signals V_(PL) synchronously with frequency ofvoltage produced in secondary winding 4 c of transformer 4; and anintegration circuit of a resistor 61 and integral capacitor 62 forproducing ramp signals V_(RP) whose inclination is inverted every halfcycle of pulse signal V_(PL) from operational amplifier 60 wherein ajunction of resistor 61 and integral capacitor 62 is connected to areference potential side (the left end in FIG. 8) of current detectingresistor 52. Inverted and non-inverted input terminals − and + ofoperational amplifier 60 are connected respectively to secondary winding4 c of transformer 4 and ground in secondary side circuit. In operation,operational amplifier 60 produces rectangular pulse signals V_(PL) ofthe alternating polarity shown in FIG. 9(B) with frequency of voltageproduced on secondary winding 4 c of transformer 4 so that pulse signalsV_(PL) from operational amplifier 60 are supplied to integral capacitor62 through resistor 61 to charge and discharge integral capacitor 62with a time constant determined by the product of a resistance value ofresistor 61 and capacitance of integral capacitor 62. Accordingly,integral capacitor 62 produces at a junction of resistor 61 and integralcapacitor 62 ramp signals V_(RP) shown in FIG. 9(C) synchronizing withfrequency of voltage developed on secondary winding 4 c of transformer4. Thus, operational amplifier 60, resistor 61 and integral capacitor 62provide a ramp signal generator for producing ramp signals V_(RP)proportional to voltage corresponding to excitation current flowingthrough primary winding 4 a of transformer. Other components in FIG. 8are substantially similar to those in the converter shown in FIG. 4.

In the circuit shown in FIG. 8, current detecting transformer 51 detectselectric current I_(Q2) flowing through primary side circuit when secondmain MOS-FET 3 is turned on, and then current detecting resistor 52converts detected electric current I_(Q2) into voltage V_(DT) relativethereto produced across detecting resistor 52. In this case, detectedvoltage V_(DT) across current detecting resistor 52 fluctuates inproportion to electric current detected by current detecting transformer51 over reference potential of ramp signal V_(RP) voltage on integralcapacitor 62. Specifically, there is produced a superimposed signalV_(RP)+V_(DT) shown in FIG. 9(D) at detection potential side (right sideend in FIG. 8) of current detecting resistor 52 since ramp signal V_(RP)shown in FIG. 9(C) on integral capacitor 62 is applied on the left endof current detecting resistor 52 which simultaneously detects thevoltage V_(DT) shown in FIG. 9(A). Composite voltage V_(RP)+V_(DT) ondetecting potential side of current detecting resistor 52 is applied toan inverted input terminal − of second comparator 57 through second DCbias power supply 54 so that inverted input terminal − of secondcomparator 57 receives composite voltage V_(RP)+V_(DT) shifted topositive side by bias voltage V_(BS2) of second DC bias power supply 54.In other words, as shown in FIG. 9(D), second comparator 57 comparescomposite voltage V_(RP)+V_(DT) on detection potential side of currentdetecting resistor 52 with bias voltage V_(BS) of second DC bias powersupply 54 relatively shifted to negative side. When composite voltageV_(RP)+V_(DT) drops below bias voltage V_(BS2) of second DC bias powersupply 54 as shown in FIG. 9(D), second comparator 57 produces secondsynchronous drive pulse signals V_(SC2) of high voltage level shown inFIG. 9(E) to gate terminal of second rectifying MOS-FET 8 through secondbuffer amplifier 58 to turn second rectifying MOS-FET 8 on.

On the other hand, current detecting transformer 51 detects electriccurrent I_(Q1) flowing through primary side circuit when first mainMOS-FET 2 is turned on, and current detecting resistor 50 convertsdetected electric current I_(Q1) into voltage V_(DT) equivalent thereto.At the moment, produced across current detecting resistor 52 is detectedvoltage which fluctuates proportionately to amount of detected currentby current detecting transformer 51 over reference potential of rampsignal V_(RP) voltage on integral capacitor 62. Specifically, compositevoltage V_(RP)+V_(DT) shown in FIG. 9(D) appears at detection potentialend (right side end in FIG. 8) of current detecting resistor 52 becauseintegral capacitor 62 retains ramp signal V_(RP) voltage shown in FIG.9(C) and coincidentally current detecting resistor 52 picks out detectedvoltage V_(DT) shown in FIG. 9(A). Then, composite voltage V_(RP)+V_(DT)on detection potential end of current detecting resistor 52 is appliedthrough first DC bias power supply 53 to non-inverted input terminal +of first comparator 55 which compares composite voltage V_(RP)+V_(DT)with ground zero volt applied to inverted input terminal − of firstcomparator 55. In other words, non-inverted input terminal + of firstcomparator 55 receives composite voltage V_(RP)+V_(DT) moved to negativeside by biasing voltage V_(BS1) of first DC bias power supply 53 sothat, as shown in FIG. 9(D), first comparator 55 compares compositevoltage V_(RP)+V_(DT) with biasing voltage V_(BS1) of first DC biaspower supply 53. When composite voltage V_(RP)+V_(DT) rises over biasingvoltage V_(BS1) of first DC bias power supply 53 as shown in FIG. 9(D),first comparator 55 produces first synchronous drive pulse signalV_(SC1) through first buffer amplifier 56 to gate terminal of firstrectifying MOS-FET 7 to turn first rectifying MOS-FET 7 on. Other basicoperations in the DC-DC converter of synchronous rectification typeshown in FIG. 8 than the aforesaid operation are substantially similarto those in the DC-DC converter shown in FIG. 1, and further detaileddescription on other operations is omitted.

In the third embodiment of the present invention, as ramp signals V_(RP)on integral capacitor 62 has the substantially similar voltage waveformto that of excitation current flowing through primary winding 4 a oftransformer 4, ramp signals V_(RP) can cancel or offset excitationcurrent component contained in electric current I_(Q1), I_(Q2) inprimary side circuit detected by current detector 51 by comparingcomposite signal V_(RP)+V_(DT) with biasing voltages V_(BS1) and V_(BS2)of first and second DC biasing power supplies 53 and 54. Accordingly,first and second rectifying MOS-FETs 7 and 8 can efficiently be turnedon synchronously with resonance current component only in electriccurrents I_(Q1) and I_(Q2) flowing in primary side circuit and exactlyin proportion to rectified output currents I_(S1) and I_(S2) flowingthrough secondary side circuit. Also, as first and second DC biasingpower supplies 53 and 54 may be of any optional bias voltage generatorscapable of producing bias voltages V_(BS1) and V_(BS2) for covering aelectric current range lower than excitation current component throughtransformer 4, it is advantageous to adopt lower biased voltage thanthat in the first embodiment. The third embodiment may be modified insubstantially similar manners as in the first embodiment shown in FIG.5. Specifically, when first and second comparators 55 and 57 are drivenwith a power supply for producing a single output, a separate bias powersupply 59 shown in FIG. 10 is connected to each input terminal forreference voltage of first and second comparators 55 and 57 to biasground zero volt of reference potential to positive side by power supply59 and up to a level that does not exceed any either allowable inputvoltage limitation of first and second comparators 55 and 57. In thecircuit shown in FIG. 10, operational amplifier 60 as a ramp signalgenerator is driven by an additional drive power supply 63. Not shown,but first and second DC biasing power supplies 53 and 54 may beconnected in a similar circuit configuration to that shown in FIG. 1.

In lieu of operational amplifier 60, resistor 61 and integral capacitor62 shown in FIG. 8, a fourth embodiment of the DC-DC converter ofsynchronous rectification type shown in FIG. 11, comprises a waveformshaper 64 as waveform shaping means for converting pulse signalsgenerated from an oscillator 22 in control circuit 21 into ramp signalsV_(RP) whose inclination is inverted every half cycle of pulse signals.An output terminal of waveform shaper 64 is connected to referencepotential side of current detecting resistor 52, and first and secondbuffer amplifiers 56 and 58 issue output signals V_(SC1) and V_(SC2)through first and second capacitors 29 and 30 and first and second pulsetransformers 31 and 34 to each gate terminal of first and secondrectifying MOS-FETs 7 and 8. Also, connected between each input terminalfor reference voltage of first and second comparators 55 and 57 andground in primary side circuit of the converter shown in FIG. 11 is abias power supply 59 for driving first and second comparators 55 and 57with bias power supply 59 for producing a single output. Othercomponents than the foregoing are substantially similar to those in theconverter shown in FIG. 8. As primary and secondary side circuits oftransformer 4 are electrically insulated from each other by virtue offirst and second pulse transformers 31 and 34 in the fourth embodiment,it is advantageous that mutual interference hardly occurs betweenprimary and secondary side circuits. Operations of the converter shownin FIG. 11 are substantially similar to those shown in FIG. 8, anddetailed description thereon is omitted.

In lieu of current detecting transformer 51 shown in FIG. 11, a fifthembodiment of the DC-DC converter of synchronous rectification typeshown in FIG. 12 comprises a shunt capacitor 65 and a transfer resistor66 connected in series and in parallel to current resonance capacitor 5;and a resistor 67 connected between a junction of shunt capacitor 65 andtransfer resistor 66 and a junction of first and second DC biasing powersupplies 53 and 54 wherein shunt capacitor 65, transfer resistor 66 andresistor 67 cooperate to form a current detector. The converter furthercomprises a resistor 68 connected between waveform shaper 64 andjunction of first and second DC biasing power supplies 53 and 54; and abias power supply 69 and a resistor 70 connected in series between ajunction of first and second DC biasing power supplies 53 and 54 andground in primary side circuit wherein first and second DC biasing powersupplies 53 and 54 are connected with adverse polarities to each other;and inverted and non-inverted input terminals − and + are replaced infirst and second comparators 55 and 57. Other components than the abovecomponents are substantially similar to those in the converter shown inFIG. 11. In the fifth embodiment, when electric current flows throughcurrent resonance capacitor 5 in primary side circuit, a minor dividedcurrent flows through shunt capacitor 65 so that transfer resistor 66converts divided current into a relative voltage which are in turnsuperimposed first and second DC biasing power supplies 53 and 54through resistor 67. Accordingly, the converter of FIG. 12 is beneficialin that it can be made with more inexpensive capacitors and resistorsfor current detector than current detecting transformer 51 shown in FIG.11, and that electric currents I_(Q1) and I_(Q2) flowing through primaryside circuit can efficiently be sensed with lesser power loss.Operations of the converter shown in FIG. 12 are essentially similar tothose of the converter shown in FIG. 8, and detailed explanation isomitted.

Embodiments of the present invention may be modified and varied infurther various ways without limitation to the foregoing fiveembodiments. By way of example, the converter shown in FIG. 5 can beredesigned as illustrated in FIG. 13 exhibiting a DC-DC converter ofsynchronous rectification type which comprises an additional currentresonance capacitor 37 connected between a junction of current resonancecapacitor 5 and primary winding 4 a of transformer 4 and drain terminalof second main MOS-FET 3; an additional voltage pseudo resonancecapacitor 38 connected between drain and source terminals of second mainMOS-FET 3; and an external current resonance reactor or coil 39connected in series to primary winding 4 a, in place of leakageinductance 4 e of transformer 4 as a current resonance reactor in FIG. 1wherein connection of first and second rectifying MOS-FETs 7 and 8 ischanged from negative output terminal to positive output terminal; firstand second DC biasing power supplies 53 and 54 are connected with theadverse polarities; and inverted and non-inverted input terminals −and + are replaced in first and second comparators 55 and 57. Operationsof the converter shown in FIG. 13 are substantially similar to those inthe converter shown in FIG. 5 except the differences that the on-periodsof first and second synchronous drive pulse signals V_(SC1) and V_(SC2)are changed with each other and levels of the drive circuits aredifferent each other because rectified output currents I_(S1) and I_(S2)flows in secondary side circuit in the opposite directions from those inFIG. 5. Accordingly, the converter shown in FIG. 13 can producesubstantially similar functions and effects as those obtained in thefirst embodiment. Also, same or similar modifications to thoseabove-mentioned can be made to first embodiments of the invention shownin FIGS. 1 and 4 and to second to fifth embodiments of the invention. Inaddition, in lieu of first and second output rectifying diodes 9 and 10in secondary side circuit, each of first to fifth embodiments mayutilize diodes integrated in first and second rectifying MOS-FETs 7 and8 between drain and source terminals. Moreover, each of first to fifthembodiments may be of full-bridge type, push-pull type or forward typein primary side circuit of transformer in place of half-bridge type.Also, secondary side circuit of transformer 4 may utilize a half-waverectifying circuit.

INDUSTRIAL APPLICABILITY

The present invention is in particular effectively applicable to currentresonant DC-DC converter of synchronous rectification type.

1. A DC-DC converter of synchronous rectification type comprising atleast one main switching element and a primary winding of a transformerfor forming a primary side circuit connected to a DC power source; atleast one rectifying switching element for forming a secondary sidecircuit connected between an electric load and a secondary windingelectromagnetically coupled to said primary winding of said transformerto drive said rectifying switching element synchronously with theswitching operation of said main switching element in order to supply DCoutput through said secondary side circuit to said load; a currentdetector for detecting electric current flowing through said primaryside circuit; biasing means for producing a greater bias voltage thanvoltage corresponding to excitation current through said transformer;and a comparator for driving said rectifying switching element whendetected voltage by current detector exceeds the biased voltage by saidbiasing means.
 2. A DC-DC converter of synchronous rectification typecomprising at least one main switching element and a primary winding ofa transformer for forming a primary side circuit connected to a DC powersource; at least one rectifying switching element for forming asecondary side circuit connected between an electric load and asecondary winding electromagnetically coupled to said primary winding ofsaid transformer to drive said rectifying switching elementsynchronously with the switching operation of said main switchingelement in order to supply DC output through said secondary side circuitto said load; a current detector for detecting electric current flowingthrough said primary side circuit; biasing means for producing a biasvoltage; a ramp signal generator for producing ramp signals inproportion to voltage corresponding to excitation current flowingthrough said transformer; and a comparator for driving said rectifyingswitching element when said detected voltage by said current detectorexceeds voltage of superimposed signal of biased voltage and ramp signalof said ramp voltage generator.
 3. A DC-DC converter of synchronousrectification type comprising at least one main switching element and aprimary winding of a transformer for forming a primary side circuitconnected to a DC power source; at least one rectifying switchingelement for forming a secondary side circuit connected between anelectric load and a secondary winding electromagnetically coupled tosaid primary winding of said transformer to drive said rectifyingswitching element synchronously with the switching operation of saidmain switching element in order to supply DC output through saidsecondary side circuit to said load; a current detector for detectingelectric current flowing through said primary side circuit; biasingmeans for producing a bias voltage; a ramp signal generator forproducing ramp signals in proportion to voltage corresponding toexcitation current flowing through said transformer; and a comparatorfor driving said rectifying switching element when superimposed voltageof said detected voltage by said current detector and ramp signal fromsaid ramp voltage generator exceeds biased voltage by biasing means. 4.A DC-DC converter of synchronous rectification type of claim 2 or 3,wherein said ramp signal generator comprises an integration circuitconnected to a secondary winding of said transformer or a winding forproducing voltage corresponding to the voltage on said secondary windingfor producing ramp signals whose inclination is inverted every halfcycle of voltage applied on said winding.
 5. A DC-DC converter ofsynchronous rectification type of claim 2 or 3, wherein said ramp signalgenerator comprises a synchronizing signal generator connected to asecondary winding of said transformer or a winding for producing voltagecorresponding to the voltage on said secondary winding for producingpulse signals in synchronization with frequency of voltage on thewinding; and an integration circuit for producing ramp signals whoseinclination is inverted every half cycle of pulse signals from saidsynchronizing signal generator.
 6. A DC-DC converter of synchronousrectification type of claim 2 or 3, wherein said ramp signal generatorcomprises a waveform shaper for converting pulse signals generated froman oscillator into ramp signals whose inclination is inverted every halfcycle of said output pulse signals, said pulse signals from saidoscillator providing a datum of switching frequency for said mainswitching element.